Last Updated on 2026-03-07 by researcher
TCFは24bitカウンターで動作しクロックソースとしてPLL(最大80MHz)が指定できる。NCO(Numerically Controlled Oscillator)による整数分周に対応してることが特徴かな。
【サンプル】
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#include "avr8_tcf.h" void sample(void) { /* 周波数生成 */ Tcf::begin(1000000, Tcf::WGMODE_FRQ, Tcf::CLKSEL_CLKPER); Tcf::output(Tcf::CMP0); Tcf::run(); /* NCO Pulse */ Tcf::begin(1000000, Tcf::WGMODE_NCOPF, Tcf::CLKSEL_CLKPER); Tcf::output(Tcf::CMP0); Tcf::run(); /* NCO Fixed Duty-Cycle */ Tcf::begin(1000000, Tcf::WGMODE_NCOFDC, Tcf::CLKSEL_CLKPER); Tcf::output(Tcf::CMP0); Tcf::run(); /* PWM8 */ Tcf::begin(1000000, Tcf::WGMODE_PWM8, Tcf::CLKSEL_CLKPER); Tcf::output(Tcf::CMP0); Tcf::pwmduty(Tcf::CMP0, Tcf::PWM_MAX_COUNT >> 1); Tcf::run(); } |
【ライブラリ】
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/* avr8_tcf.h - TCF Driver for Microchip AVR8 Series Copyright (c) 2026 Sasapea's Lab. All right reserved. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <https://www.gnu.org/licenses/>. */ #pragma once #include "avr8_config.h" #include "avr8_clock.h" #if defined(TCF0) class Tcf { public: static const uint8_t PWM_MAX_COUNT; /* CMP */ typedef enum { CMP0, CMP1, } CMP; /* Clock Select */ typedef enum { CLKSEL_CLKPER = TCF_CLKSEL_CLKPER_gc, /* Peripheral Clock */ CLKSEL_EVENT = TCF_CLKSEL_EVENT_gc, /* Event as clock source */ CLKSEL_OSCHF = TCF_CLKSEL_OSCHF_gc, /* Internal High Frequency Oscillator */ CLKSEL_OSC32K = TCF_CLKSEL_OSC32K_gc, /* Internal 32.768 kHz Oscillator */ CLKSEL_PLL = TCF_CLKSEL_PLL_gc /* PLL */ } CLKSEL; /* Clock Prescaler select */ typedef enum { PRESC_DIV1 = TCF_PRESC_DIV1_gc, /* Runs directly on Clock Source */ PRESC_DIV2 = TCF_PRESC_DIV2_gc, /* Divide clock source by 2 */ PRESC_DIV4 = TCF_PRESC_DIV4_gc, /* Divide clock source by 4 */ PRESC_DIV8 = TCF_PRESC_DIV8_gc, /* Divide clock source by 8 */ PRESC_DIV16 = TCF_PRESC_DIV16_gc, /* Divide clock source by 16 */ PRESC_DIV32 = TCF_PRESC_DIV32_gc, /* Divide clock source by 32 */ PRESC_DIV64 = TCF_PRESC_DIV64_gc, /* Divide clock source by 64 */ PRESC_DIV128 = TCF_PRESC_DIV128_gc /* Divide clock source by 128 */ } PRESC; /* Waveform Generation Mode select */ typedef enum { WGMODE_FRQ = TCF_WGMODE_FRQ_gc, /* Frequency */ WGMODE_NCOPF = TCF_WGMODE_NCOPF_gc, /* Numerically Controlled Oscillator Pulse-Frequency */ WGMODE_NCOFDC = TCF_WGMODE_NCOFDC_gc, /* Numerically Controlled Oscillator Fixed Duty Cycle */ WGMODE_PWM8 = TCF_WGMODE_PWM8_gc /* 8-bit PWM */ } WGMODE; /* Waveform Generation Pulse Length select */ typedef enum { WGPULSE_CLK1 = TCF_WGPULSE_CLK1_gc, /* High pulse duration is 1 clock period */ WGPULSE_CLK2 = TCF_WGPULSE_CLK2_gc, /* High pulse duration is 2 clock period */ WGPULSE_CLK4 = TCF_WGPULSE_CLK4_gc, /* High pulse duration is 4 clock period */ WGPULSE_CLK8 = TCF_WGPULSE_CLK8_gc, /* High pulse duration is 8 clock period */ WGPULSE_CLK16 = TCF_WGPULSE_CLK16_gc, /* High pulse duration is 16 clock period */ WGPULSE_CLK32 = TCF_WGPULSE_CLK32_gc, /* High pulse duration is 32 clock period */ WGPULSE_CLK64 = TCF_WGPULSE_CLK64_gc, /* High pulse duration is 64 clock period */ WGPULSE_CLK128 = TCF_WGPULSE_CLK128_gc /* High pulse duration is 128 clock period */ } WGPULSE; /* Waveform Output # Polarity select */ typedef enum { WOPOL_NORMAL = TCF_WO0POL_NORMAL_gc, /* Waveform output set on update and cleared on match */ WOPOL_INVERSE = TCF_WO0POL_INVERSE_gc /* Waveform output cleared on update and set on match */ } WOPOL; /* Compare # Event Generation select */ typedef enum { CMPEV_PULSE = TCF_CMP0EV_PULSE_gc, /* Event is generated as pulse */ CMPEV_WAVEFORM = TCF_CMP0EV_WAVEFORM_gc /* Waveform is used as event output */ } CMPEV; /* Event Action A select */ typedef enum { EVACTA_RESTART = TCF_EVACTA_RESTART_gc, /* Restart Counter */ EVACTA_BLANK = TCF_EVACTA_BLANK_gc /* Mask waveform output to '0' */ } EVACTA; /* TCF.INTCTRL bit masks and bit positions */ typedef enum { INTCTRL_OVF = TCF_OVF_bm, /* Overflow bit mask. */ INTCTRL_CMP0 = TCF_CMP0_bm, /* Compare 0 Interrupt Enable bit mask. */ INTCTRL_CMP1 = TCF_CMP1_bm /* Compare 1 Interrupt Enable bit mask. */ } INTCTRL; /* TCF.INTFLAGS bit masks and bit positions */ typedef enum { INTFLAGS_OVF = TCF_OVF_bm, /* Overflow bit mask. */ INTFLAGS_CMP0 = TCF_CMP0_bm, /* Compare 0 Interrupt Enable bit mask. */ INTFLAGS_CMP1 = TCF_CMP1_bm /* Compare 1 Interrupt Enable bit mask. */ } INTFLAGS; /* Type of Callback Function */ typedef void (*callback_t)(INTFLAGS flags); Tcf(void) { } /* virtual */ ~Tcf(void) { } static bool begin(uint32_t freq, WGMODE wgmode = WGMODE_FRQ, CLKSEL clksel = CLKSEL_CLKPER) { if (freq) { uint32_t clk = frequency(clksel); uint32_t div, max; switch (wgmode) { case WGMODE_FRQ: clk >>= 1; /* fall through */ case WGMODE_PWM8: max = wgmode == WGMODE_PWM8 ? PWM_MAX_COUNT : MAX_COUNT; div = (clk / freq + max) / (max + 1); for (uint8_t i = 0; i < 8; ++i) { if (div <= (uint8_t)(1 << i)) { begin(wgmode, clksel, (PRESC)(i << TCF_PRESC_gp)); clk = clk / (1 << i) / freq - 1; if (wgmode == WGMODE_PWM8) pwmperiod(clk); else period(clk); return true; } } begin(wgmode, clksel, PRESC_DIV128); if (wgmode == WGMODE_PWM8) pwmperiod(PWM_MAX_COUNT); else period(MAX_COUNT); break; case WGMODE_NCOFDC: clk >>= 1; /* fall through */ case WGMODE_NCOPF: clk = (uint64_t)freq * (MAX_COUNT + 1UL) / clk; max = wgmode == WGMODE_NCOPF ? (MAX_COUNT + 1UL) >> 1 : MAX_COUNT + 1UL; if (clk >= max) { begin(wgmode, clksel, PRESC_DIV1); period(max); wgpulse(WGPULSE_CLK1); break; } if (clk) { for (uint8_t i = 0; i < 8; ++i, clk >>= 1) { if (clk < max) { begin(wgmode, clksel, (PRESC)(i << TCF_PRESC_gp)); period(clk); clk = (MAX_COUNT + 1UL) / clk; for (i = 7; i > 0; --i) { if (clk >= (uint16_t)(1 << (i + 1))) break; } wgpulse((WGPULSE)(i << TCF_WGPULSE_gp)); return true; } } } begin(wgmode, clksel, PRESC_DIV128); period(2); wgpulse(WGPULSE_CLK128); break; } } return false; } static void begin(WGMODE wgmode, CLKSEL clksel, PRESC presc) { end(); TCF0.DBGCTRL = 0; TCF0.INTFLAGS = 0xFF; TCF0.INTCTRL = 0; TCF0.EVCTRL = 0; TCF0.CTRLB = clksel | wgmode; reg32(STATUS_CNTBUSY , 0); reg32(STATUS_CMP0BUSY, 0); reg(STATUS_CTRLCBUSY, 0); reg(STATUS_CTRLDBUSY, 0); reg(STATUS_CTRLABUSY, presc); _frequency = 0; _callback = 0; } static void end(void) { reg(STATUS_CTRLABUSY, 0); } static uint32_t frequency(void) { if (_frequency == 0) _frequency = frequency((CLKSEL)(TCF0.CTRLB & TCF_CLKSEL_gm)) >> ((TCF0.CTRLA & TCF_PRESC_gm) >> TCF_PRESC_gp); return _frequency; } static void runstdby(bool enable = true) { reg(STATUS_CTRLABUSY, enable ? TCF_RUNSTDBY_bm : 0, TCF_RUNSTDBY_bm); } static void wgpulse(WGPULSE wgpulse = WGPULSE_CLK1) { reg(STATUS_CTRLCBUSY, wgpulse, TCF_WGPULSE_gm); } static void output(CMP cmp, bool enable = true, WOPOL polarity = WOPOL_NORMAL) { reg(STATUS_CTRLCBUSY, (enable ? TCF_WO0EN_bm << cmp : 0) | (polarity << cmp), (TCF_WO0EN_bm | TCF_WO0POL_bm) << cmp); } static void event(CMP cmp, CMPEV event = CMPEV_PULSE) { /* Enable-protected */ TCF0.CTRLB = (TCF0.CTRLB & ~(TCF_CMP0EV_bm << cmp)) | (event << cmp); } static void evctrl(bool cntei = true, EVACTA act = EVACTA_RESTART, bool filter = false) { /* Enable-protected */ TCF0.EVCTRL = (filter ? TCF_FILTERA_bm : 0) | act | (cntei ? TCF_CNTAEI_bm : 0); } static void period(uint32_t value) { if ((TCF0.CTRLB & TCF_WGMODE_gm) != TCF_WGMODE_PWM8_gc) reg32(STATUS_CMP0BUSY, value); } static void pwmperiod(uint8_t value) { if ((TCF0.CTRLB & TCF_WGMODE_gm) == TCF_WGMODE_PWM8_gc) reg(STATUS_PERBUSY, value); } static void pwmduty(CMP cmp, uint8_t duty) { if ((TCF0.CTRLB & TCF_WGMODE_gm) == TCF_WGMODE_PWM8_gc) reg((STATUS)(STATUS_CMP0BUSY << cmp), (uint16_t)duty * TCF0.CNT1 / PWM_MAX_COUNT); } static void run(void) { reg(STATUS_CTRLABUSY, TCF_ENABLE_bm, TCF_ENABLE_bm); } static void restart(void) { command(CMD_RESTART); } static void callback(callback_t func) { _callback = func; } static void interrupt(INTCTRL ctrl, bool enable = true) { if (enable) { TCF0.INTFLAGS = ctrl; #if CONFIG_TCF_ISR TCF0.INTCTRL |= ctrl; #endif } else { #if CONFIG_TCF_ISR TCF0.INTCTRL &= ~ctrl; #endif TCF0.INTFLAGS = ctrl; } } static void dbgctrl(bool dbgrun = true) { TCF0.DBGCTRL = dbgrun ? TCF_DBGRUN_bm : 0; } static void poll(void) { #if !CONFIG_TCF_ISR isr(); #endif } private: static const uint32_t MAX_COUNT; /* Command select */ typedef enum { CMD_NONE = TCF_CMD_NONE_gc, /* No command */ CMD_UPDATE = TCF_CMD_UPDATE_gc, /* Force update */ CMD_RESTART = TCF_CMD_RESTART_gc /* Force restart */ } CMD; /* TCF.STATUS bit masks and bit positions */ typedef enum { STATUS_CTRLABUSY = TCF_CTRLABUSY_bm, /* Control A Synchronization Busy bit mask. */ STATUS_CTRLCBUSY = TCF_CTRLCBUSY_bm, /* Control B Synchronization Busy bit mask. */ STATUS_CTRLDBUSY = TCF_CTRLDBUSY_bm, /* Control D Synchronization Busy bit mask. */ STATUS_CNTBUSY = TCF_CNTBUSY_bm, /* Counter Synchronization Busy bit mask. */ STATUS_PERBUSY = TCF_PERBUSY_bm, /* Period Synchronization Busy bit mask. (valid only in the PWM8 mode) */ STATUS_CMP0BUSY = TCF_CMP0BUSY_bm, /* Compare 0 Synchronization Busy bit mask. */ STATUS_CMP1BUSY = TCF_CMP1BUSY_bm, /* Compare 1 Synchronization Busy bit mask. (valid only in the PWM8 mode) */ } STATUS; static uint32_t _frequency; static callback_t _callback; #if CONFIG_TCF_ISR friend void tcf_isr(void); #endif static inline void isr(void) { uint8_t flags = TCF0.INTFLAGS = TCF0.INTFLAGS; if (flags && _callback) _callback((INTFLAGS)flags); } static void update(void) { command(CMD_UPDATE); } static void command(CMD cmd) { reg(STATUS_CTRLDBUSY, cmd); } static void reg(STATUS status, uint8_t value, uint8_t mask = 0xFF) { value &= mask; wait(status); switch (status) { case STATUS_CTRLABUSY: TCF0.CTRLA = (TCF0.CTRLA & ~mask) | value; break; case STATUS_CTRLCBUSY: TCF0.CTRLC = (TCF0.CTRLC & ~mask) | value; break; case STATUS_CTRLDBUSY: TCF0.CTRLD = value; break; case STATUS_CNTBUSY : TCF0.CNT0 = value; break; case STATUS_PERBUSY : TCF0.CNT1 = value; break; case STATUS_CMP0BUSY : TCF0.CMP0 = value; break; case STATUS_CMP1BUSY : TCF0.CMP1 = value; break; default: break; } if (status != STATUS_CTRLDBUSY) update(); } static void reg32(STATUS status, uint32_t value) { wait(status); switch (status) { case STATUS_CNTBUSY : TCF0.CNT = value; break; case STATUS_CMP0BUSY: TCF0.CMP = value; break; default: break; } /* A write or read access to byte 2 (offset + 0x2) triggers a new synchronization. */ } static void wait(STATUS status) { while (TCF0.STATUS & status) yield(); } static uint32_t frequency(CLKSEL clksel) { switch (clksel) { case CLKSEL_CLKPER: return Clock::frequency(); case CLKSEL_OSCHF : return Fuse::OSCCFG::frequency(); case CLKSEL_OSC32K: return 32768; case CLKSEL_PLL : return Clock::pllfreq(); default: break; } return 0; } }; #endif |
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/* avr8_tcf.h - TCF Driver for Microchip AVR8 Series Copyright (c) 2026 Sasapea's Lab. All right reserved. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <https://www.gnu.org/licenses/>. */ #include "avr8_tcf.h" #if defined(TCF0) const uint32_t Tcf::MAX_COUNT = 0xFFFFFF; const uint8_t Tcf::PWM_MAX_COUNT = 0xFF; uint32_t Tcf::_frequency; Tcf::callback_t Tcf::_callback; #if CONFIG_TCF_ISR inline void tcf_isr(void) { Tcf::isr(); } ISR(TCF0_INT_vect) { tcf_isr(); } #endif #endif |
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