前回投稿のRi5-RP1用のGPIOライブラリをさらにGPCLK対応してみた。
最初は全く動かなくてハマリまくってしまったがクロック・レジスタの構造体の定義が間違っていただけだった。v(-_-;)
GPCLKを最大３出力できるがGPCLK1/2はSDIO関連で利用する？っぽい感じなので使えるけど使うのはお勧めではないかも。
GPCLKの分周比が16ビットなのとPWMと同じXOSCクロックを使用するため出力周波数は763Hz～50MHzまでとなる。
しかし、GPIOで50MHzの出力は無理そうな気もするのでもっと低いクロックを使いたかったのだがGPCLK0/1/2で共通使用できるクロックはXOSCぐらいしか見つけられなかった．．．
使い方は簡単で次のように出力ピンと周波数(Hz)を指定する。利用可能な出力ピンはgetGPCLKChannel()を見るべし！
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rp1.outputGPCLK(PIN_GPCLK, 1000); |
【サンプル】
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#include <unistd.h> #include "rp1-gpio.h" #define PIN_LED 26 #define PIN_PWM 19 #define PIN_GPCLK 4 RP1_GPIO rp1; int main(int argc, char **argv) { rp1.begin(); rp1.pinMode(PIN_LED, rp1.OUTPUT); rp1.analogWrite(PIN_PWM, rp1.PWM0_FREQ, rp1.PWM0_FREQ / 2); rp1.outputGPCLK(PIN_GPCLK, 1000); while (1) { rp1.digitalWrite(PIN_LED, rp1.TOGGLE); usleep(500000); // 0.5秒待機 } rp1.end(); return 0; } |
【ライブラリ】
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/* rp1-gpio.h - Raspberry Pi RP1 GPIO Driver Copyright (c) 2024 Sasapea's Lab. All right reserved. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <https://www.gnu.org/licenses/>. */ #pragma once #include <stdio.h> #include <stdint.h> #include <stdbool.h> #include <string.h> #include <fcntl.h> #include <unistd.h> #include <sys/mman.h> #include <sys/ioctl.h> #include <linux/gpio.h> class RP1_GPIO { public: typedef enum { CHIP_UNKNOWN = -1, CHIP_BCM2835, CHIP_BCM2711, CHIP_RP1, } ChipType; static ChipType getGpioChipType(uint32_t *lines = nullptr) { int fd = open("/dev/gpiochip0", 0); if (fd != -1) { struct gpiochip_info cinfo; if (ioctl(fd, GPIO_GET_CHIPINFO_IOCTL, &cinfo) != -1) { close(fd); if (strcmp("pinctrl-rp1", cinfo.label) == 0) { if (lines) *lines = cinfo.lines; return CHIP_RP1; } else if (strcmp("pinctrl-bcm2711", cinfo.label) == 0) { if (lines) *lines = cinfo.lines; return CHIP_BCM2711; } else if (strcmp("pinctrl-bcm2835", cinfo.label) == 0) { if (lines) *lines = cinfo.lines; return CHIP_BCM2835; } } close(fd); } return CHIP_UNKNOWN; } typedef uint32_t pin_size_t; typedef enum { LOW, HIGH, TOGGLE, // only digitalWrite() } PinStatus; typedef enum { INPUT, OUTPUT, OPEN_DRAIN, OPEN_SOURCE, DISABLE, } PinMode; typedef enum { PULL_DISABLE, PULL_UP, PULL_DOWN, } PinPull; typedef enum { DVDD_3V3, // voltage to 3.3V (DVDD >= 2V5) DVDD_1V8, // voltage to 1.8V (DVDD <= 1V8) } PinVoltage; typedef enum { DRIVE_2MA, // Drive strength. 2mA DRIVE_4MA, // Drive strength. 4mA DRIVE_8MA, // Drive strength. 8mA DRIVE_12MA, // Drive strength. 12mA } PinDrive; typedef enum { PinFunc_A0, // SPI[0/1], PWM[0/1/2/3], GPCLK[0/1/2] PinFunc_A1, // DPI PinFunc_A2, // UART[1/2/3/4], MIPI[0/1], I2S[0] PinFunc_A3, // I2C[0/1/2/3], PWM[2/3], GPCLK[0/1] PinFunc_A4, // UART[0], AUDIO[0], I2S[1] PinFunc_A5, // SYS_RIO, PinFunc_A6, // PROC_RIO, PinFunc_A7, // PIO, PinFunc_A8, // SPI[2/3/4/5], GPCLK[1], PinFunc_RIO = PinFunc_A5, PinFunc_NONE = 0x1F, } PinFunc; typedef enum { INMODE_PERI, INMODE_INVPERI, INMODE_LOW, INMODE_HIGH, } PinInput; typedef enum { OEMODE_PERI, OEMODE_INVPERI, OEMODE_DISABLE, OEMODE_ENABLE, } PinEnable; typedef enum { OUTMODE_PERI, OUTMODE_INVPERI, OUTMODE_LOW, OUTMODE_HIGH, } PinOutput; typedef enum { IRQ_NORMAL, IRQ_INVERT, IRQ_DRIVE_LOW, IRQ_DRIVE_HIGH, } PinInterrupt; typedef enum { PWM_MODE_ZERO, PWM_MODE_TRAILING_EDGE, PWM_MODE_DOUBLE_EDGE, PWM_MODE_PDM, PWM_MODE_SERIALISER_MSB, PWM_MODE_PPM, PWM_MODE_LEADING_EDGE, PWM_MODE_SERIALISER_LSB, } PWM_MODE; static constexpr uint32_t PWM0_MAX_FREQ = 76800000; static constexpr uint32_t PWM0_FREQ = 50000000; private: typedef volatile uint32_t rw_reg_t; typedef const volatile uint32_t ro_reg_t; enum { ATOM_RW , ATOM_XOR, ATOM_SET, ATOM_CLR, }; public: // // IO_BANK0: GPIO_STATUS Register // typedef union { struct { ro_reg_t _rsv1_ : 8; // Reserved. ro_reg_t OUTFROMPERI : 1; // [0x00] output signal from selected peripheral, before register overide is applied ro_reg_t OUTTOPAD : 1; // [0x00] output signal to pad after register overide is applied ro_reg_t _rsv2_ : 2; // Reserved. ro_reg_t OEFROMPERI : 1; // [0x00] output enable from selected peripheral, before register overide is applied ro_reg_t OETOPAD : 1; // [0x00] output enable to pad after register overide is applied ro_reg_t _rsv3_ : 2; // Reserved. ro_reg_t INISDIRECT : 1; // [0x00] input signal from pad, goes directly to the selected peripheral without filtering or override ro_reg_t INFROMPAD : 1; // [0x00] input signal from pad, before filtering and override are applied ro_reg_t INFILTERED : 1; // [0x00] input signal from pad, after filtering is applied but before override, not valid if inisdirect=1 ro_reg_t INTOPERI : 1; // [0x00] input signal to peripheral, after filtering and override are applied, not valid if inisdirect=1 ro_reg_t EVENT_EDGE_LOW : 1; // [0x00] Input pin has seen falling edge. Clear with ctrl_irqreset ro_reg_t EVENT_EDGE_HIGH : 1; // [0x00] Input pin has seen rising edge. Clear with ctrl_irqreset ro_reg_t EVENT_LEVEL_LOW : 1; // [0x00] Input pin is Low ro_reg_t EVENT_LEVEL_HIGH : 1; // [0x00] Input pin is high ro_reg_t EVENT_F_EDGE_LOW : 1; // [0x00] Input pin has seen a filtered falling edge. Clear with ctrl_irqreset ro_reg_t EVENT_F_EDGE_HIGH : 1; // [0x00] Input pin has seen a filtered rising edge. Clear with ctrl_irqreset ro_reg_t EVENT_DB_LEVEL_LOW : 1; // [0x00] Debounced input pin is low ro_reg_t EVENT_DB_LEVEL_HIGH : 1; // [0x00] Debounced input pin is high ro_reg_t IRQCOMBINED : 1; // [0x00] interrupt to processors, after masking ro_reg_t IRQTOPROC : 1; // [0x00] interrupt to processors, after mask and override is applied } bit; ro_reg_t reg; } GPIO_STATUS; // // IO_BANK0: GPIO_CTRL Register // typedef union { struct { rw_reg_t FUNCSEL : 5; // [0x1f] Function select. 31 == NULL. See GPIO function table for available functions. rw_reg_t F_M : 7; // [0x04] Filter/debounce time constant M rw_reg_t OUTOVER : 2; // [0x00] 0x0=drive output from peripheral signal selected by funcsel // 0x1=drive output from inverse of peripheral signal selected by funcsel // 0x2=drive output low // 0x3=drive output high rw_reg_t OEOVER : 2; // [0x00] 0x0=drive output enable from peripheral signal selected by funcsel // 0x1=drive output enable from inverse of peripheral signal selected by funcsel // 0x2=disable output // 0x3=enable output rw_reg_t INOVER : 2; // [0x00] 0x0=don’t invert the peri input // 0x1=invert the peri input // 0x2=drive peri input low // 0x3=drive peri input high ro_reg_t _rsv1_ : 2; // Reserved. rw_reg_t IRQMASK_EDGE_LOW : 1; // [0x00] Masks the edge low interrupt into the interrupt output rw_reg_t IRQMASK_EDGE_HIGH : 1; // [0x00] Masks the edge high interrupt into the interrupt output rw_reg_t IRQMASK_LEVEL_LOW : 1; // [0x00] Masks the level low interrupt into the interrupt output rw_reg_t IRQMASK_LEVEL_HIGH : 1; // [0x00] Masks the level high interrupt into the interrupt output rw_reg_t IRQMASK_F_EDGE_LOW : 1; // [0x00] Masks the filtered edge low interrupt into the interrupt output rw_reg_t IRQMASK_F_EDGE_HIGH : 1; // [0x00] Masks the filtered edge high interrupt into the interrupt output rw_reg_t IRQMASK_DB_LEVEL_LOW : 1; // [0x00] Masks the debounced level low interrupt into the interrupt output rw_reg_t IRQMASK_DB_LEVEL_HIGH: 1; // [0x00] Masks the debounced level high interrupt into the interrupt output rw_reg_t IRQRESET : 1; // [0x00] 0x0=do nothing, 0x1=reset the interrupt edge detector ro_reg_t _rsv2_ : 1; // Reserved. rw_reg_t IRQOVER : 2; // [0x00] 0x0=don’t invert the interrupt // 0x1=invert the interrupt // 0x2=drive interrupt low // 0x3=drive interrupt high } bit; rw_reg_t reg; } GPIO_CTRL; private: // // IO_BANK0: GPIO Register // typedef struct { GPIO_STATUS STATUS; GPIO_CTRL CTRL; } gpio_reg_t; // // IO_BANK0: PROCx/PCIE Interrupt Register // typedef struct { rw_reg_t INTE; // Interrupt Enable rw_reg_t INTF; // Interrupt Force ro_reg_t INTS; // Interrupt status after masking & forcing } gpio_irq_t; // // IO_BANK0: Registers // typedef struct { union { struct { gpio_reg_t PINS[28]; // GPIO[0-27] gpio_reg_t _rsv_[4]; // Reserved. ro_reg_t INTR; // Raw Interrupts gpio_irq_t PROC[2]; // Interrupt for PROC[0,1] gpio_irq_t PCIE; // Interrupt for PCIE } REG; uint8_t _rsv_[0x1000]; } ATOM[4]; } IO_BANK0; // // PADS_BANK0: GPIO0, GPIO1, …, GPIO26, GPIO27 Registers // typedef union { struct { rw_reg_t SLEWFAST: 1; // [0x00] Slew rate control. 1 = Fast, 0 = Slow rw_reg_t SCHMITT : 1; // [0x01] Enable schmitt trigger rw_reg_t PDE : 1; // [varies] Pull down enable rw_reg_t PUE : 1; // [varies] Pull up enable rw_reg_t DRIVE : 2; // [0x01] Drive strength. 0=2mA, 1=4mA, 2=8mA, 3=12mA rw_reg_t IE : 1; // [0x00] Input enable rw_reg_t OD : 1; // [0x01] Output disable. Has priority over output enable from peripherals } bit; rw_reg_t reg; } PADS_CTRL; // // PADS_BANK0: Registers. // typedef struct { union { struct { // // VOLTAGE_SELECT Register // union { struct { rw_reg_t VOLTAGE_SELECT: 1; // [0x00] Voltage select. Per bank control // 0x0=Set voltage to 3.3V (DVDD >= 2V5) // 0x1=Set voltage to 1.8V (DVDD <= 1V8) } bit; rw_reg_t reg; } VOLT; // // GPIO0, GPIO1, …, GPIO26, GPIO27 Registers // PADS_CTRL PADS[28]; } REG; uint8_t _rsv_[0x1000]; } ATOM[4]; } PADS_BANK0; // // SYS_RIO0: Registers. // typedef struct { union { struct { rw_reg_t OUT; // controls the GPIO output drive rw_reg_t OE; // controls the GPIO output drive enable ro_reg_t IN; // samples the GPIO inputs directly ro_reg_t SYNC_IN; // samples the GPIO inputs, each synchronised with a 2-stage synchroniser to clk_sys } REG; uint8_t _rsv_[0x1000]; } ATOM[4]; } SYS_RIO0; // // GPCLK OE Register (undocumented) // typedef union { struct { rw_reg_t OE: 6; } bit; rw_reg_t reg; } GPCLK_CTRL; // // CLOCK Register (undocumented) // static constexpr uint32_t AUX_SEL = 1; typedef struct { union { struct { rw_reg_t SRC : 5; rw_reg_t AUXSRC : 5; rw_reg_t B10 : 1; rw_reg_t ENABLE : 1; ro_reg_t _rsv1_ : 4; rw_reg_t B16 : 1; rw_reg_t B17 : 1; ro_reg_t _rsv2_ : 2; rw_reg_t B20 : 1; ro_reg_t _rsv3_ : 3; ro_reg_t STATUS1 : 1; ro_reg_t _rsv4_ : 3; ro_reg_t STATUS2 : 1; ro_reg_t _rsv5_ : 3; } bit; rw_reg_t reg; } CTRL; rw_reg_t DIV_INT; rw_reg_t DIV_FRAC; rw_reg_t SEL; // set AUX_SEL } CLOCK_CTRL; // // FC Register (undocumented) // typedef struct { rw_reg_t REF_KHZ; rw_reg_t MIN_KHZ; rw_reg_t MAX_KHZ; rw_reg_t DELAY; rw_reg_t INTERVAL; rw_reg_t SRC; union { struct { ro_reg_t _rsv1_ : 4; rw_reg_t DONE : 1; ro_reg_t _rsv2_ : 3; rw_reg_t RUNNING: 1; } bit; rw_reg_t reg; } STATUS; rw_reg_t RESULT; } FC_CTRL; // // CLOCKS_MAIN: (undocumented) // typedef struct { GPCLK_CTRL GP_CTRL; CLOCK_CTRL _rsv1_; CLOCK_CTRL SYS; CLOCK_CTRL SLOW_SYS; CLOCK_CTRL _rsv2_; CLOCK_CTRL DMA; CLOCK_CTRL UART; CLOCK_CTRL ETH; CLOCK_CTRL PWM0; CLOCK_CTRL PWM1; CLOCK_CTRL AUDIO_IN; CLOCK_CTRL AUDIO_OUT; CLOCK_CTRL I2S; CLOCK_CTRL MIPI0_CFG; CLOCK_CTRL MIPI1_CFG; CLOCK_CTRL PCIE_AUX; CLOCK_CTRL USBH0_MICROFRAME; CLOCK_CTRL USBH1_MICROFRAME; CLOCK_CTRL USBH0_SUSPEND; CLOCK_CTRL USBH1_SUSPEND; CLOCK_CTRL ETH_TSU; CLOCK_CTRL ADC; CLOCK_CTRL SDIO_TIMER; CLOCK_CTRL SDIO_ALT_SRC; CLOCK_CTRL GP[6]; CLOCK_CTRL _rsv3_; CLOCK_CTRL _rsv4_; CLOCK_CTRL _rsv5_; CLOCK_CTRL SYS_RESUS; CLOCK_CTRL SLOW_SYS_RESUS; ro_reg_t _rsv6_; FC_CTRL FC[8]; } CLOCKS_MAIN; // // CLK_GP0: AUXSRC (undocumented) // typedef enum { CLK_GP0_XOSC, CLK_GP0_CLKSRC_GP1, CLK_GP0_CLKSRC_GP2, CLK_GP0_CLKSRC_GP3, CLK_GP0_CLKSRC_GP4, CLK_GP0_CLKSRC_GP5, CLK_GP0_PLL_SYS, CLK_GP0_PLL_AUDIO, CLK_GP0_RSV1, CLK_GP0_RSV2, CLK_GP0_CLK_I2S, CLK_GP0_CLK_ADC, CLK_GP0_RSV3, CLK_GP0_RSV4, CLK_GP0_RSV5, CLK_GP0_CLK_SYS, } CLK_GP0; // // CLK_GP1: AUXSRC (undocumented) // typedef enum { CLK_GP1_CLK_SDIO_TIMER, CLK_GP1_CLKSRC_GP0, CLK_GP1_CLKSRC_GP2, CLK_GP1_CLKSRC_GP3, CLK_GP1_CLKSRC_GP4, CLK_GP1_CLKSRC_GP5, CLK_GP1_PLL_SYS_PRI_PH, CLK_GP1_RSV1, CLK_GP1_RSV2, CLK_GP1_RSV3, CLK_GP1_CLK_ADC, CLK_GP1_CLK_DPI, CLK_GP1_CLK_PWM0, CLK_GP1_RSV4, CLK_GP1_RSV5, CLK_GP1_RSV6, } CLK_GP1; // // CLK_GP2: AUXSRC (undocumented) // typedef enum { CLK_GP2_CLK_SDIO_ALTSRC, CLK_GP2_CLKSRC_GP0, CLK_GP2_CLKSRC_GP1, CLK_GP2_CLKSRC_GP3, CLK_GP2_CLKSRC_GP4, CLK_GP2_CLKSRC_GP5, CLK_GP2_PLL_SYS_SEC, CLK_GP2_RSV1, CLK_GP2_PLL_VIDEO, CLK_GP2_CLK_AUDIO_IN, CLK_GP2_CLK_DPI, CLK_GP2_CLK_PWM0, CLK_GP2_CLK_PWM1, CLK_GP2_CLK_MIPI0_DPI, CLK_GP2_CLK_MIPI1_CFG, CLK_GP2_CLK_SYS, } CLK_GP2; // // CLK_GP3: AUXSRC (undocumented) // typedef enum { CLK_GP3_XOSC, CLK_GP3_CLKSRC_GP0, CLK_GP3_CLKSRC_GP1, CLK_GP3_CLKSRC_GP2, CLK_GP3_CLKSRC_GP4, CLK_GP3_CLKSRC_GP5, CLK_GP3_RSV1, CLK_GP3_RSV2, CLK_GP3_PLL_VIDO_PRI_PH, CLK_GP3_CLK_AUDIO_OUTPUT, CLK_GP3_RSV3, CLK_GP3_RSV4, CLK_GP3_CLK_MIPI1_DPI, CLK_GP3_RSV5, CLK_GP3_RSV6, CLK_GP3_RSV7, } CLK_GP3; // // CLK_GP4: AUXSRC (undocumented) // typedef enum { CLK_GP4_XOSC, CLK_GP4_CLKSRC_GP0, CLK_GP4_CLKSRC_GP1, CLK_GP4_CLKSRC_GP2, CLK_GP4_CLKSRC_GP3, CLK_GP4_CLKSRC_GP5, CLK_GP4_RSV1, CLK_GP4_PLL_VIDO_SEC, CLK_GP4_RSV2, CLK_GP4_RSV3, CLK_GP4_RSV4, CLK_GP4_CLK_MIPI0_CFG, CLK_GP4_CLK_UART, CLK_GP4_RSV5, CLK_GP4_RSV6, CLK_GP4_CLK_SYS, } CLK_GP4; // // CLK_GP5: AUXSRC (undocumented) // typedef enum { CLK_GP5_XOSC, CLK_GP5_CLKSRC_GP0, CLK_GP5_CLKSRC_GP1, CLK_GP5_CLKSRC_GP2, CLK_GP5_CLKSRC_GP3, CLK_GP5_CLKSRC_GP4, CLK_GP5_RSV1, CLK_GP5_PLL_VIDO_SEC, CLK_GP5_CLK_ETH_TSU, CLK_GP5_RSV2, CLK_GP5_CLK_VEC, CLK_GP5_RSV3, CLK_GP5_RSV4, CLK_GP5_RSV5, CLK_GP5_RSV6, CLK_GP5_RSV7, } CLK_GP5; // // CLK_PWM0: AUXSRC (undocumented) // typedef enum { CLK_PWM0_PLL_AUDIO_PRI_PH, /* only rpi-6.1.y */ CLK_PWM0_PLL_VIDEO_SEC, CLK_PWM0_XOSC, CLK_PWM0_CLKSRC_GP0, /* only rpi-6.6.y */ CLK_PWM0_CLKSRC_GP1, /* only rpi-6.6.y */ CLK_PWM0_CLKSRC_GP2, /* only rpi-6.6.y */ CLK_PWM0_CLKSRC_GP3, /* only rpi-6.6.y */ CLK_PWM0_CLKSRC_GP4, /* only rpi-6.6.y */ CLK_PWM0_CLKSRC_GP5, /* only rpi-6.6.y */ } CLK_PWM0; // // CLK_PWM1: AUXSRC (undocumented) // typedef enum { CLK_PWM1_PLL_AUDIO_PRI_PH, /* only rpi-6.1.y */ CLK_PWM1_PLL_VIDEO_SEC, CLK_PWM1_XOSC, CLK_PWM1_CLKSRC_GP0, /* only rpi-6.6.y */ CLK_PWM1_CLKSRC_GP1, /* only rpi-6.6.y */ CLK_PWM1_CLKSRC_GP2, /* only rpi-6.6.y */ CLK_PWM1_CLKSRC_GP3, /* only rpi-6.6.y */ CLK_PWM1_CLKSRC_GP4, /* only rpi-6.6.y */ CLK_PWM1_CLKSRC_GP5, /* only rpi-6.6.y */ } CLK_PWM1; // // PWM: Registers. // typedef struct { // // GLOBAL_CTRL Register. Global control bits // union { struct { rw_reg_t CHAN_EN : 4; // [0x00] 1=Enable the respective PWM channel in the mode set by the CHANx_CTRL registers, 0=Channel disabled ro_reg_t _rsv_ : 27; // Reserved. rw_reg_t SET_UPDATE: 1; // [0x00] To prevent mis-sampling of multi-bit bus signals in the PWM clock domain, // this bit should be used to trigger a settings update. // This ensures that all PWM channel settings update on the same PWM clock cycle. // Write 1 to trigger a settings update to the block. Self clears to 0. // This bit affects the chan*_en bits, chan*_phase, chan*_ctrl and common_range registers. // Writes to the *_duty and *_range registers have an integral update strobe // and writes take effect on the next counter overflow of the respective PWM channel. } bit; rw_reg_t reg; } GLOBAL_CTRL; // // FIFO_CTRL Register. FIFO thresholding and status // union { struct { ro_reg_t LEVEL : 5; // [0x00] Number of available words in the FIFO rw_reg_t FLUSH : 1; // [0x00] Assert to flush FIFO ro_reg_t FLUSH_DONE: 1; // [0x00] FIFO flush completed in the PWM clock domain ro_reg_t _rsv1_ : 4; // Reserved. rw_reg_t THRESHOLD : 5; // [0x00] Threshold for the comparator. DREQ is asserted when level <= threshold. rw_reg_t DWELL_TIME: 5; // [0x02] Delay in number of bus cycles before successive DREQs are generated. // Used to account for system bus latency in write data arriving at the FIFO. ro_reg_t _rsv2_ : 10; // Reserved. rw_reg_t DREQ_EN : 1; // [0x00] 1=Generate DMA request signals to the DMA controller // 0=Don’t generate request signals - the dreq_active interrupt is unaffected. } bit; rw_reg_t reg; } FIFO_CTRL; // // COMMON_RANGE Register. // rw_reg_t COMMON_RANGE; // [0x00] Counter range register for channels that are set to use channel binding // // COMMON_DUTY Register. // rw_reg_t COMMON_DUTY; // [0x00] Counter compare register for channels that are set to use channel binding and are not set to use the common FIFO // // DUTY_FIFO Register. // rw_reg_t DUTY_FIFO; // [0x00] 32-bit interface to a 128-bit backed duty cycle FIFO // In round-robin fashion, 32-bit writes to this address are sequentially packed // as 32*n-bit words that are pushed into the duty cycle FIFO. N varies as per the // number of enabled channels set to use the FIFO. A distributor checks which channels // are enabled and using the FIFO, and writes the 32-bit words accordingly // // CHANx Registers. // struct { // // CHANx_CTRL Register // union { struct { rw_reg_t MODE : 3; // [0x00] PWM generation mode // 0x0=Generates 0 // 0x1=Trailing-edge mark-space PWM modulation // 0x2=Phase-correct mark-space PWM modulation // 0x3=Pulse-density encoded output // 0x4=MSB Serialiser output. // 0x5=Pulse position modulated output - a single high pulse is transmitted per cycle. // 0x6=Leading-edge mark-space PWM modulation // 0x7=LSB Serialiser output. rw_reg_t INVERT : 1; // [0x00] 1=Invert the output bit rw_reg_t BIND : 1; // [0x00] 1=Bind Channel x to the common_range and common_duty/duty_fifo registers // 0=Channel x uses chanx_range and chanx_duty rw_reg_t USEFIFO : 1; // [0x00] 1=Use the duty_fifo. Note: setting bind=0 and usefifo=1 will lead to unpredictable operation // 0=Use the duty cycle register common_duty/chanx_duty rw_reg_t SDM : 1; // [0x00] 1=Use sigma-delta noise shaping modulator. In conjunction with sdm_bitwidth, // treat the duty cycle as a 16-bit signed truncation of the 32 bit duty cycle value and quantise // to (sdm_bitwidth+1)-bits. The resulting quantisation noise is filtered using a 2nd-order loop. // 0=Bypass modulator rw_reg_t DITHER : 1; // [0x00] 1=When SDM mode is used, add a 1-bit LSB dither inside the noise shaping loop to suppress idle tones // 0=No dither applied rw_reg_t FIFO_POP_MASK: 1; // [0x01] 0=Counter overflow events do not generate FIFO pop events // 1=Counter overflow events generate FIFO pop events ro_reg_t _rsv1_ : 3; // Reserved. rw_reg_t SDM_BITWIDTH : 4; // [0x00] Quantise the 16-bit input to a (sdm_bitwidth+1)-bit output. 0=1-bit output. rw_reg_t SDM_BIAS : 16; // [0x00] Unsigned offset to be added to the output PWM code generated by the sigma-delta modulator. } bit; rw_reg_t reg; } CTRL; // // CHANx_RANGE Register. // rw_reg_t RANGE; // [0x00] Channel x counter range // // CHANx_PHASE Register. // rw_reg_t PHASE; // [0x00] Channel x counter phase offset register // This register preloads the internal counter such that phase offsets between // channels can be introduced. Do not set higher than the respective range register. // // CHANx_DUTY Register. // rw_reg_t DUTY; // [0x00] Channel x counter compare register } CHAN[4]; // // INTR Register. Raw Interrupts // union { struct { rw_reg_t FIFO_UNDERFLOW: 1; // [0x00] rw_reg_t FIFO_OVERFLOW : 1; // [0x00] ro_reg_t FIFO_EMPTY : 1; // [0x00] ro_reg_t FIFO_FULL : 1; // [0x00] ro_reg_t DREQ_ACTIVE : 1; // [0x00] rw_reg_t CHAN_RELOAD : 4; // [0x00] } bit; rw_reg_t reg; } INTR; // // INTE Register. Interrupt Enable // union { struct { rw_reg_t FIFO_UNDERFLOW: 1; // [0x00] rw_reg_t FIFO_OVERFLOW : 1; // [0x00] rw_reg_t FIFO_EMPTY : 1; // [0x00] rw_reg_t FIFO_FULL : 1; // [0x00] rw_reg_t DREQ_ACTIVE : 1; // [0x00] rw_reg_t CHAN_RELOAD : 4; // [0x00] } bit; rw_reg_t reg; } INTE; // // INTF Register. Interrupt Force // union { struct { rw_reg_t FIFO_UNDERFLOW: 1; // [0x00] rw_reg_t FIFO_OVERFLOW : 1; // [0x00] rw_reg_t FIFO_EMPTY : 1; // [0x00] rw_reg_t FIFO_FULL : 1; // [0x00] rw_reg_t DREQ_ACTIVE : 1; // [0x00] rw_reg_t CHAN_RELOAD : 4; // [0x00] } bit; rw_reg_t reg; } INTF; // // INTS Register. Interrupt status after masking & forcing // union { struct { ro_reg_t FIFO_UNDERFLOW: 1; // [0x00] ro_reg_t FIFO_OVERFLOW : 1; // [0x00] ro_reg_t FIFO_EMPTY : 1; // [0x00] ro_reg_t FIFO_FULL : 1; // [0x00] ro_reg_t DREQ_ACTIVE : 1; // [0x00] ro_reg_t CHAN_RELOAD : 4; // [0x00] } bit; rw_reg_t reg; } INTS; } PWM; static constexpr size_t CLOCKS_MAIN_OFFS = 0x18000; static constexpr size_t PWM0_OFFS = 0x98000; static constexpr size_t PWM1_OFFS = 0x9C000; static constexpr size_t IO_BANK0_OFFS = 0xD0000; static constexpr size_t SYS_RIO0_OFFS = 0xE0000; static constexpr size_t PADS_BANK0_OFFS = 0xF0000; static constexpr size_t PERIPHERALS_SIZE = 0x10000 + PADS_BANK0_OFFS; static constexpr size_t PERIPHERALS_BASE = 0x1F00000000; void *_periferals = MAP_FAILED; CLOCKS_MAIN *_clocks_main = nullptr; PWM *_pwm0 = nullptr; PWM *_pwm1 = nullptr; IO_BANK0 *_io_bank0 = nullptr; SYS_RIO0 *_sys_rio0 = nullptr; PADS_BANK0 *_pads_bank0 = nullptr; PinMode _pin_mode[28] = {}; bool isValidPin(pin_size_t pin) { return (_periferals != MAP_FAILED) && (pin < sizeof(_pin_mode) / sizeof(_pin_mode[0])); } public: RP1_GPIO(void) { } virtual ~RP1_GPIO(void) { end(); } ChipType begin(void) { ChipType chip = getGpioChipType(); if (chip == CHIP_RP1) { end(); int fd = open("/dev/mem", O_RDWR | O_SYNC); if (fd != -1) { if ((_periferals = mmap(0, PERIPHERALS_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_LOCKED, fd, PERIPHERALS_BASE)) != MAP_FAILED) { _clocks_main = (CLOCKS_MAIN *)((char *)_periferals + CLOCKS_MAIN_OFFS); _pwm0 = (PWM *)((char *)_periferals + PWM0_OFFS ); _pwm1 = (PWM *)((char *)_periferals + PWM1_OFFS ); _io_bank0 = (IO_BANK0 *)((char *)_periferals + IO_BANK0_OFFS ); _sys_rio0 = (SYS_RIO0 *)((char *)_periferals + SYS_RIO0_OFFS ); _pads_bank0 = (PADS_BANK0 *)((char *)_periferals + PADS_BANK0_OFFS ); } close(fd); return chip; } } return CHIP_UNKNOWN; } void end(void) { if (_periferals != MAP_FAILED) munmap(_periferals, PERIPHERALS_SIZE); _periferals = MAP_FAILED; _clocks_main = nullptr; _pwm0 = nullptr; _pwm1 = nullptr; _io_bank0 = nullptr; _sys_rio0 = nullptr; _pads_bank0 = nullptr; } void setPadsVoltage(PinVoltage mode = DVDD_3V3) { if (isValidPin(0)) _pads_bank0->ATOM[ATOM_RW].REG.VOLT.bit.VOLTAGE_SELECT = mode; } void setSlewFast(pin_size_t pin, bool enable = false) { if (isValidPin(pin)) _pads_bank0->ATOM[ATOM_RW].REG.PADS[pin].bit.SLEWFAST = enable; } void setSchmittTrigger(pin_size_t pin, bool enable = true) { if (isValidPin(pin)) _pads_bank0->ATOM[ATOM_RW].REG.PADS[pin].bit.SCHMITT = enable; } void setDriveStrength(pin_size_t pin, PinDrive mode = DRIVE_4MA) { if (isValidPin(pin)) _pads_bank0->ATOM[ATOM_RW].REG.PADS[pin].bit.DRIVE = mode; } void setPullUpDown(pin_size_t pin, PinPull mode = PULL_DISABLE) { if (isValidPin(pin)) { PADS_CTRL &pads = _pads_bank0->ATOM[ATOM_RW].REG.PADS[pin]; switch (mode) { default: case PULL_DISABLE: pads.bit.PDE = 0; pads.bit.PUE = 0; break; case PULL_UP: pads.bit.PDE = 0; pads.bit.PUE = 1; break; case PULL_DOWN: pads.bit.PDE = 1; pads.bit.PUE = 0; break; } } } void setInterrupt(pin_size_t pin, PinInterrupt mode = IRQ_NORMAL) { if (isValidPin(pin)) _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.IRQOVER = mode; } void resetEvent(pin_size_t pin) { if (isValidPin(pin)) _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.IRQRESET = 1; } void setEventMask(pin_size_t pin, GPIO_CTRL mask) { if (isValidPin(pin)) { GPIO_CTRL &gpio = _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL; gpio.bit.IRQMASK_EDGE_LOW = mask.bit.IRQMASK_EDGE_LOW; gpio.bit.IRQMASK_EDGE_HIGH = mask.bit.IRQMASK_EDGE_HIGH; gpio.bit.IRQMASK_LEVEL_LOW = mask.bit.IRQMASK_LEVEL_LOW; gpio.bit.IRQMASK_LEVEL_HIGH = mask.bit.IRQMASK_LEVEL_HIGH; gpio.bit.IRQMASK_F_EDGE_LOW = mask.bit.IRQMASK_F_EDGE_LOW; gpio.bit.IRQMASK_F_EDGE_HIGH = mask.bit.IRQMASK_F_EDGE_HIGH; gpio.bit.IRQMASK_DB_LEVEL_LOW = mask.bit.IRQMASK_DB_LEVEL_LOW; gpio.bit.IRQMASK_DB_LEVEL_HIGH = mask.bit.IRQMASK_DB_LEVEL_HIGH; } } GPIO_STATUS getPinStatus(pin_size_t pin) { static const GPIO_STATUS EMPTY = {}; return isValidPin(pin) ? _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].STATUS : EMPTY; } void setFuncSel(pin_size_t pin, PinFunc func = PinFunc_NONE) { if (isValidPin(pin)) _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.FUNCSEL = func; } void setFilterDebounceTime(pin_size_t pin, uint8_t m = 4) { if (isValidPin(pin)) _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.F_M = m; } void setInputMode(pin_size_t pin, PinInput mode = INMODE_PERI) { if (isValidPin(pin)) _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.INOVER = mode; } void setOutputEnable(pin_size_t pin, PinEnable mode = OEMODE_PERI) { if (isValidPin(pin)) _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.OEOVER = mode; } void setOutputMode(pin_size_t pin, PinOutput mode = OUTMODE_PERI) { if (isValidPin(pin)) _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.OUTOVER = mode; } void pinMode(pin_size_t pin, PinMode mode) { if (isValidPin(pin)) { GPIO_CTRL &gpio = _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL; PADS_CTRL &pads = _pads_bank0->ATOM[ATOM_RW].REG.PADS[pin]; pads.bit.IE = 0; pads.bit.OD = 1; switch (_pin_mode[pin] = mode) { default: case INPUT: _sys_rio0->ATOM[ATOM_CLR].REG.OE = (1 << pin); gpio.bit.FUNCSEL = PinFunc_RIO; pads.bit.IE = 1; break; case OUTPUT: _sys_rio0->ATOM[ATOM_SET].REG.OE = (1 << pin); gpio.bit.FUNCSEL = PinFunc_RIO; pads.bit.IE = 1; pads.bit.OD = 0; break; case OPEN_DRAIN: digitalWrite(pin, _sys_rio0->ATOM[ATOM_RW].REG.OUT & (1 << pin) ? HIGH : LOW); _sys_rio0->ATOM[ATOM_CLR].REG.OUT = (1 << pin); gpio.bit.FUNCSEL = PinFunc_RIO; pads.bit.IE = 1; pads.bit.OD = 0; break; case OPEN_SOURCE: digitalWrite(pin, _sys_rio0->ATOM[ATOM_RW].REG.OUT & (1 << pin) ? HIGH : LOW); _sys_rio0->ATOM[ATOM_SET].REG.OUT = (1 << pin); gpio.bit.FUNCSEL = PinFunc_RIO; pads.bit.IE = 1; pads.bit.OD = 0; break; case DISABLE: gpio.bit.FUNCSEL = PinFunc_NONE; break; } } } void digitalWrite(pin_size_t pin, PinStatus value) { if (isValidPin(pin)) { int mode; switch (_pin_mode[pin]) { default: if (value == TOGGLE) mode = ATOM_XOR; else if (value) mode = ATOM_SET; else mode = ATOM_CLR; _sys_rio0->ATOM[mode].REG.OUT = (1 << pin); break; case OPEN_DRAIN: if (value == TOGGLE) mode = ATOM_XOR; else if (value) mode = ATOM_CLR; else mode = ATOM_SET; _sys_rio0->ATOM[mode].REG.OE = (1 << pin); break; case OPEN_SOURCE: if (value == TOGGLE) mode = ATOM_XOR; else if (value) mode = ATOM_SET; else mode = ATOM_CLR; _sys_rio0->ATOM[mode].REG.OE = (1 << pin); break; } } } PinStatus digitalRead(pin_size_t pin, bool sync = false) { rw_reg_t val = 0; if (isValidPin(pin)) val = (sync ? _sys_rio0->ATOM[ATOM_RW].REG.SYNC_IN : _sys_rio0->ATOM[ATOM_RW].REG.IN) & (1 << pin); return val ? HIGH : LOW; } private: void enablePWM0Clock(void) { if (_clocks_main->PWM0.CTRL.bit.ENABLE == 0) { _clocks_main->PWM0.DIV_INT = 1; _clocks_main->PWM0.DIV_FRAC = 0; _clocks_main->PWM0.SEL = AUX_SEL; _clocks_main->PWM0.CTRL.bit.SRC = 0; _clocks_main->PWM0.CTRL.bit.AUXSRC = CLK_PWM0_XOSC; _clocks_main->PWM0.CTRL.bit.ENABLE = 1; } } int getPWM0Channel(pin_size_t pin, PinFunc &alt) { if (isValidPin(pin)) { switch (pin) { case 12: alt = PinFunc_A0; return 0; case 13: alt = PinFunc_A0; return 1; case 14: alt = PinFunc_A0; return 2; case 15: alt = PinFunc_A0; return 3; case 18: alt = PinFunc_A3; return 2; case 19: alt = PinFunc_A3; return 3; } } return -1; } public: void analogWrite(pin_size_t pin, uint32_t range, uint32_t duty, bool invert = false, PWM_MODE mode = PWM_MODE_TRAILING_EDGE) { PinFunc alt; int ch = getPWM0Channel(pin, alt); if (ch >= 0) { if (range == 0) { // channel enable ? if ((_pwm0->GLOBAL_CTRL.bit.CHAN_EN & (1 << ch)) != 0) { // disable output _pads_bank0->ATOM[ATOM_RW].REG.PADS[pin].bit.OD = 1; _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.FUNCSEL = PinFunc_NONE; // set pwm0 mode _pwm0->CHAN[ch].CTRL.bit.MODE = PWM_MODE_ZERO; // disable pwm0 channel _pwm0->GLOBAL_CTRL.bit.CHAN_EN &= ~(1 << ch); // update pwm channel _pwm0->GLOBAL_CTRL.bit.SET_UPDATE = 1; } } else { // enable pwm0 clock enablePWM0Clock(); // set pwm0 mode _pwm0->CHAN[ch].CTRL.bit.MODE = mode; _pwm0->CHAN[ch].CTRL.bit.INVERT = invert; _pwm0->CHAN[ch].RANGE = range; _pwm0->CHAN[ch].PHASE = 0; _pwm0->CHAN[ch].DUTY = duty > range ? range : duty; // enable output _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.FUNCSEL = alt; _pads_bank0->ATOM[ATOM_RW].REG.PADS[pin].bit.OD = 0; // enable pwm0 channel _pwm0->GLOBAL_CTRL.bit.CHAN_EN |= (1 << ch); // update pwm channel _pwm0->GLOBAL_CTRL.bit.SET_UPDATE = 1; } } } private: int getGPCLKChannel(pin_size_t pin, PinFunc &alt) { if (isValidPin(pin)) { switch (pin) { case 4: alt = PinFunc_A0; return 0; case 5: alt = PinFunc_A0; return 1; case 6: alt = PinFunc_A0; return 2; case 18: alt = PinFunc_A8; return 1; case 20: alt = PinFunc_A3; return 0; case 21: alt = PinFunc_A3; return 1; } } return -1; } public: void outputGPCLK(pin_size_t pin, uint32_t freq) { PinFunc alt; int ch = getGPCLKChannel(pin, alt); if (ch >= 0) { if (freq == 0) { // output enable ? if ((_clocks_main->GP_CTRL.bit.OE & (1 << ch)) != 0) { // disable output _pads_bank0->ATOM[ATOM_RW].REG.PADS[pin].bit.OD = 1; _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.FUNCSEL = PinFunc_NONE; _clocks_main->GP_CTRL.bit.OE &= ~(1 << ch); } } else { static constexpr int CLKSRC[] = { CLK_GP0_XOSC, CLK_GP1_CLK_PWM0, CLK_GP2_CLK_PWM0 }; uint64_t div = ((uint64_t)PWM0_FREQ << 16) / freq; if (div > UINT32_MAX) div = UINT32_MAX; else if (div < UINT16_MAX + 1) div = UINT16_MAX + 1; // enable GPCLK if (ch) enablePWM0Clock(); _clocks_main->GP[ch].DIV_INT = div >> 16; _clocks_main->GP[ch].DIV_FRAC = div << 16; _clocks_main->GP[ch].SEL = AUX_SEL; _clocks_main->GP[ch].CTRL.bit.SRC = 0; _clocks_main->GP[ch].CTRL.bit.AUXSRC = CLKSRC[ch]; _clocks_main->GP[ch].CTRL.bit.ENABLE = 1; // enable output _clocks_main->GP_CTRL.bit.OE |= (1 << ch); _io_bank0->ATOM[ATOM_RW].REG.PINS[pin].CTRL.bit.FUNCSEL = alt; _pads_bank0->ATOM[ATOM_RW].REG.PADS[pin].bit.OD = 0; } } } }; |